Recently, an increase in clock speed in a device such as a CPU is being realized. Such a CPU with a high clock speed is likely to generate high frequency noises.
Generally, in a power supply line connecting a device such as a CPU to a power supply for supplying driving power to the device, a capacitor with a relatively large capacitance is utilized for bypassing high frequency noises generated in the device to the ground side (ground line side) to prevent the noises from entering the power supply.
Further, for a DC power supply, capacitors with a relatively large capacitance are connected in parallel to the output side so that the output power can be stabilized by repeating charge and discharge of the capacitors.
As a capacitor which is usable for the above-described purposes, a solid electrolytic capacitor is known.
An example of prior art solid electrolytic capacitor is disclosed in the following Patent Document 1. FIG. 26 shows the structure of the solid electrolytic capacitor disclosed in the Patent Document.
Patent Document 1: JP-A 2003-163137
The illustrated capacitor B is a resin-package-type solid electrolytic capacitor comprising a porous sintered body 90, an anode 90a, a cathode 90b, terminals 92, 93 and sealing resin 94. The porous sintered body 90 is prepared by compacting and sintering metal particles or conductive ceramic particles. As shown in FIG. 27, for example, the capacitor B is connected in parallel between a power supply 100 and a device 101. The noises generated from the device 101 are bypassed to the line of the negative pole side (the line with (−) in the figure), so that the noises are prevented from entering the power supply 100 side and influencing the power supply 100.
The capacitance of the capacitor B can be increased relatively easily by increasing the size of the porous sintered body 90. As is well known, a capacitor with a larger capacitance has a lower impedance, so that an ideal capacitor with a high capacitance has an excellent noise cancellation property for a low frequency band.
However, the capacitor B shown in FIG. 26 has equivalent series resistance Rx and equivalent series inductance Lx on the line between the anode 90a and the terminal 93 and on the line between the cathode 90b and the terminal 92, and has inherent self-resonant frequency determined by the equivalent series resistance Rx, the equivalent series inductance Lx and the equivalent capacitance C.
Therefore, although the capacitor B has a relatively low impedance and hence has sufficient noise cancellation property with respect to a certain frequency range around the self-resonant frequency, the noise cancellation property for the other ranges is not satisfactory.
Further, when the capacitor B is used for the stabilization of a DC power supply, transient response characteristics in outputting charge stored in the equivalent capacitance C of the capacitor B to the device pose a problem. Specifically, the smaller the time constant determined by the equivalent series resistance Rx and the equivalent series inductance Lx is, the more excellent the transient response characteristics are. In the structure shown in FIG. 26, the equivalent series resistance Rx and the equivalent series inductance Lx are relatively large due to the long lines between the anode 90a and the terminal 93 and between the cathode 90b and the terminal 92, so that the time constant cannot be reduced sufficiently. Therefore, sufficient transient response characteristics cannot be obtained, and there is a limitation on the high speed responsiveness.
FIG. 28 shows another example of usage of the prior art capacitor. In this example, a plurality of capacitors which are different from each other in capacitance and self resonant frequency are connected in parallel. With this arrangement, good noise cancellation property can be provided for a relatively wide frequency band, and the responsiveness can be enhanced. However, since it is difficult to adjust the characteristics such as self resonant frequency which are inherent in each capacitor, the noise cancellation property and the high speed responsiveness cannot be further enhanced. Moreover, the use of a plurality of capacitors is disadvantageous in terms of the space efficiency on a board and the cost.